1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor and a fabrication method thereof. More particularly, this application relates to a semiconductor device having a dummy pattern that prevents formation of a crack in an insulating layer and a fabrication method thereof.
2. Description of the Related Art
Semiconductor memory devices, in particular, dynamic random access memory (DRAM) devices, commonly include capacitors for storing data in unit cells. More particularly, a unit cell of a DRAM device consists of a cell capacitor and an access transistor which is directly connected to the cell capacitor. The capacitance value of the capacitor is a primary factor in its data storage capability.
With the continuing trend toward increased integration density in semiconductor devices, the device area occupied by a unit cell has been decreased dramatically. With decreased capacitor size, the capacitance of the unit cell capacitor becomes smaller, which results in a reduced capability for storing unit cell data. Specifically, under certain circumstances, a unit cell can lose the data that was stored in the cell, causing functional errors in the memory device. Therefore, it is desired that the capacitance value of a unit cell capacitor be maintained, even with reduced capacitor size due to higher integration, in order to maintain proper device function in a high-density device.
A capacitor generally comprises a storage electrode that functions as a lower electrode, a dielectric layer, and a plate electrode that functions as an upper electrode. It is well known that by increasing the surface area of a unit cell capacitor's storage electrode, an increase in the capacitance value of the unit cell capacitor can be achieved. For example, in the case of a stacked storage electrode or a cylindrical storage electrode, the capacitance of the unit cell can be increased by increasing the height of the storage electrode. Therefore, in order to form a capacitor having an increased capacitance value in the same area of a unit cell, in contemporary embodiments, a COB (Capacitor Over Bit-line) structure including a capacitor formed under a bit-line and a CUB (Capacitor Under Bit-line) structure including a capacitor formed over a bit-line are employed, with the COB structure being more popular than the CUB structure, since it results in higher capacitance values and higher integration.
However, in the case of the COB structure, increasing the height of the storage electrode can result in several problems. One of the problems is that the difference in height between a memory cell region and a peripheral region occurs because the plurality of capacitors are formed only in the memory cell region. Thereafter, when a planarizing process for an insulating layer formed on the capacitor is performed, for example, a CMP (Chemical Mechanical Polishing) process, cracking of the insulating layer can occur at the boundary between the memory cell region and the peripheral region.
FIG. 1A is a cross-sectional TEM (Transmission Electron Microscope) image illustrating a conventional method of fabricating a semiconductor device having a cylindrical storage electrode.
Referring to FIG. 1A, an insulating layer 20 is deposited on a plurality of capacitors 10 in a memory cell region and on a semiconductor substrate in a peripheral region. In order to reduce the height difference between the memory cell region and the peripheral region, a planarizing process is performed after the insulating layer 20 is conformally deposited on the semiconductor substrate including the plurality of capacitors.
FIG. 1B is a planar TEM image after the planarizing process is performed. As can be seen in a circle B of the FIG. 1B, a crack is formed in the insulating layer along the boundary between the memory cell region and the peripheral region. The crack occurs because of a groove that is formed at the boundary in circle A of the FIG. 1A as a result of the height difference between the memory cell region and the peripheral region. Such a crack can result in a functional error of the semiconductor device, in turn decreasing the reliability of the device.